The present invention relates to frequency synthesizers and, more specifically to phase locked loop (PLL) frequency synthesizers which are suitable for wireless communications.
PLL frequency synthesizers are well known in the art and are extensively used in wireless applications. Essentially, a PLL is a circuit that uses feedback to maintain an output signal in a specific phase relationship with a stable reference signal. Normally, a PLL circuit contains a minimum of 4 components:
a) a phase detector which produces output voltage proportional to the phase difference between two input signals, normally the reference signal and a frequency divider output;
b) a voltage controlled oscillator (VCO) that produces an AC output signal whose frequency is proportional to the input control voltage, normally received from the loop filter;
c) a divider that produces a signal whose frequency is a division of the input signal frequency, normally the output of the VCO; and
d) a loop filter that controls the PLL dynamics.
It should be noted that the phase detector output is fed into the loop filter for filtering before being transmitted to the VCO. The VCO output is ideally the desired output from the PLL. For frequency synthesizer applications, the VCO produces a signal with a desired frequency. This desired frequency is generally much higher than the frequency of the stable reference signal and is ideally a multiple of that reference signal. By dividing the frequency of the output of the VCO and comparing the phase of that divided signal with the phase of the reference signal, any differences in phase, and therefore in frequency, can be compensated for by the phase detector and the VCO.
It is well known that PLL circuits for frequency synthesizer applications need to be low noise and must have low sensitivity to power supply variations. A frequency synthesizer having a PLL circuit with these characteristics would produce an output which is low in both spurious tones and noise.
Current PLL designs for frequency synthesizers which produce frequencies near or above the GHz range often require the output of the VCO to be synchronized to the PLL reference signal with a repeatability error of less than 1 picosecond (10xe2x88x9212 sec). This repeatability can be impaired in the PLL or in any of its components by interference, commonly referred to as cross-talk, from either nearby circuits or from the components which actually make up the PLL. The amount of cross talk that occurs in the PLL depends on the sensitivity to power supply variations and other sources of coupling from one PLL component to another. This problem can be more severe in a highly integrated application specific integrated circuit (ASIC) or when the frequency planing of these interfering signals cannot be well controlled. Failure to meet these repeatability requirements can result in spurious output tones at the synthesizer output. Such an occurrence can possibly prevent qualification of the radio to public standards.
Given the above, cross talk is not the only source of spurious tones. Different combinations of phase detectors and dividers also produce different levels of spurious output tones at multiples of the PLL reference frequency. One method of avoiding this pitfall is the use of filters. However, such filters can be expensive. To avoid expensive filtering components, it is desirable to reduce the amplitude of these tones.
One approach to solve the problem is to use edge triggered phase detectors. This avoids the problem of obtaining a 50% duty cycle, but it also consumes more power and introduces more sensitivity to power supply variations as compared to a single gate phase detector such as an exclusive OR.
Another area of concern for PLL circuits is its power consumption. To be suitable for wireless applications, such as in battery powered cellular phones, the PLL circuit would have to consume little power. This would extend the battery life of the wireless equipment.
A further problem with current PLL circuits is encountered when analog and digital circuits are used together. In mixed analog and digital integrated circuits, it is common practice to have sensitive analog operations occur at different times from digital operations. However, different phase detectors have different phase offsets at which they lock. This phase offset can reduce the amount of xe2x80x9cquiet timexe2x80x9d available for sensitive analog operations, such as sampling in switched capacitor filters. As an example, a phase offset of 90 degrees reduces the amount of quiet time by 50%
On the other hand, a phase offset of exactly zero can also cause problems. With a phase offset of zero, the divider and the source of the reference signal can experience cross-talk or dead zone problems.
By way of explanation, it should be noted that the dead zone refers to the attribute of a phase frequency detector (PFD) to produce an output which does not steer the output over a range of phase difference between the divider output and the reference signal. It should also be noted that other phase detectors (PD) typically do not operate linearly over a range of all possible phase errors. The region of operation where the phase detection is linear is often called the phase detection window of the phase detector.
Returning to the question of phase offsets, one possible solution to the problem of phase offsets is to use XOR phase detectors. These produce a two state output with substantial spurs (tones or frequency components) at twice the reference frequency. These spurs can be removed with substantial filtering but, as noted above, at a cost of increased component count and complexity.
Another suggested solution to the above problems deal with the divider. It has been suggested that a synchronous counter can be used to perform frequency division. However, this approach has typically been rejected for applications requiring low power.
Another approach has been to use a prescaler stage and a synchronous counter stage. Dividers made up of several divider stages are more vulnerable to power supply and bias line interference. Generally, divider stages that consume less power are also more vulnerable to interference. This has been addressed in the past by resynchronizing the divider output. However, such a measure is undesirable from a power consumption point of view because the resynchronizing circuitry can consume considerable power without adding any functionality to the divider chip.
Dividers, on their own, also pose problems. Dividers employing a single synchronous divider can sometimes produce a very narrow output pulse. This narrow pulse width contains high frequency spectral content which can interfere with sensitive analog circuits on or near the same chip.
The problem has traditionally been solved by either avoiding the use of fractional-N synthesizers or by providing shielding means to isolate sources of interference from sensitive circuits. Avoiding fractional-N synthesizers avoids the need for sensitive analog components on or near the synthesizer chip. Without these sensitive components, the potential sources of interference are avoided.
From the above, it is clear that a need exists for a PLL circuit for frequency synthesizer applications that avoid the problems disclosed.
The present invention is a method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output. Thus, during the active pulse of the divider output, the analog PD is operative while during the inactive pulse the digital PFD is operative. By essentially having only one PD active at any time, problems with analog/digital mixed circuits are avoided.
In one embodiment, the invention provides a phase locked loop (PLL) frequency synthesizer comprising, a composite phase frequency detection (CPFD) having a CPFD output; a loop filter having a voltage output; a voltage controlled oscillator (VCO) having a frequency output; and a divider having a divider output, the divider output having an active pulse with a first fixed width and an inactive pulse with a second width; wherein the CPFD is coupled to receive the divider output; the CPFD is coupled to receive a reference signal from a reference signal generator; the loop filter is coupled to receive the CPFD output; the VCO is coupled to receive the voltage output, said voltage output controllably affecting the frequency output; the divider is coupled to receive the frequency output; the loop filter generates the voltage output based on the CPFD output; the CFPD output indicates a phase difference between the divider output and the reference signal; and the frequency has a frequency that is a multiple of the frequency of the divider output.
In another embodiment, there is provided a composite phase frequency detector (PFD) for determining a phase difference between a reference signal and an input signal, the composite phase frequency detector comprising: a digital PFD having a dead zone, the said dead zone being a time range when the digital PFD has no output,an analog phase detector (PD) with a PD window, and a PD output, said PD window being a time range when the analog PD operates linearly; and a converter coupled to receive both the digital PFD output and the PD output; wherein an output of the converter is the CFPD output, the digital PFD is coupled to receive the reference signal and the input signal, the analog PD is coupled to receive the reference signal and the input signal; the digital PFD output indicates a presence and a magnitude of a phase difference between the reference signal and the input signal when the digital PFD is not in the dead zone, the analog PD output is proportional to the phase difference between the reference signal and the input signal when the analog PD is within the PD window, the dead zone is within the PD window and said digital PFD output being larger in magnitude than the analog PD output when the digital PFD is not in the dead zone.
In another embodiment, the invention provides an analog phase detector (PD) for detecting differences in phase between a reference signal and an input signal, the analog PD comprising, a NOT gate coupled to receive the reference signal and having an output, a first AND gate coupled to receive the output of the NOT gate and the input signal, said first AND gate having an output, a second AND gate coupled to receive the reference signal and the input signal, said second AND gate having an output and a subtractor circuit coupled to receive the output of the first AND gate and the output of the second AND gate, said subtractor circuit having an output which is the difference between the output of the first AND gate and the output of the second AND gate,wherein the output of the subtractor is the analog PD output.
In yet another embodiment, the invention provides a digital phase frequency detector (PFD) for detecting differences in phase and frequency between a reference signal and an input signal, the digital PFD comprising, a phase frequency detector coupled to receive the reference signal and the input signal, the PFD producing a pump up signal and a pump down signal, said pump up signal and pump down signal being produced depending on the presence and magnitude of a phase difference between the input signal and the reference signal, a PFD NOT gate coupled to receive the input signal, a first PFD AND gate coupled to receive an output of the PFD NOT gate and the pump up signal from the PFD, a second PFD AND gate coupled to receive the output of the PFD NOT gate and the pump down signal from the PFD and a combiner coupled to receive the output of the first PFD AND gate and the output of the second PFD AND gate, said combiner producing the digital PFD output based on the output of the first PFD AND gate and the output of the second PFD AND gate.
In yet another embodiment, the invention provides a frequency divider for dividing the frequency of an input signal, the divider having a divider output and comprising, a 2xc3x971 multiplexer coupled to receive, a divide ratio signal; a pulse width signal; and the divider output, said multiplexer multiplexing between the divide ratio signal and the pulse width signal to produce a multiplexer output, said multiplexing being determined by the divider output; a synchronous counter coupled to receive the multiplexer output and the input signal, said counter being constructed and arranged to conduct a count down from a value determined by the multiplexer output with the input signal providing a clock signal, said counter producing a count pulse when the count down is terminated and a T flip-flop coupled to receive the count pulse from the synchronous counter and further coupled to receive the input signal as the clock signal, the T flip-flop having an output which is the divider output.
In another embodiment, the invention provides a method of compensating for and detecting phase differences between a reference signal and a subject signal with a controllable pulse width using: an analog phase detector having a phase detector window in which the analog phase detector is active during the phase detector window, the analog phase detector receiving the reference signal and the subject signal, a digital phase frequency detector having a dead zone in which the digital phase frequency detector is inactive during the dead zone, the digital phase frequency detector receiving the reference signal and the subject signal and a divider producing the subject signal with a controllable pulse width signal, the method comprising: controlling the controllable pulse width of the subject signal and synchronizing the phase detector window and the dead zone such that, the phase detector window and the dead zone are both within an active pulse of the subject signal.
In yet another embodiment, there is provided a method of compensating for and detecting phase signal differences between a reference signal and a subject signal with a pulse width, the method comprising activating a digital phase frequency detector to provide phase frequency detection between the reference signal and the subject signal during an inactive pulse of the. subject signal, activating an analog phase detector to provide phase detection between the reference signal and the subject signal during an active pulse of the subject signal.